4 ms·

Assembly? Thats for amateurs, we should move right to FPGAs

• vardump 7y ago
  To cut this short (own silicon, sand, etc.), we should just create a universe first. FPGAs are fun, though. Saving 12 microseconds (assuming gigabit and "standard" frame sizes) of latency by sending ethernet frames (that contains frame data CRC!) before you even have all of the data to send and then modifying data at the end of frame to match with whatever CRC we sent ~12000 bit times (= 12 microseconds) before.
  • mr__y 7y ago
    That seems extremely interesting to me! Would you care to tell any details about that or is it covered by NDA? I'm guessing that's something HFT related?
    • vardump 7y ago
      This was just for fun (tm). I know HFT guys pull of tricks like these, but no, this is either not difficult to pull off on an FPGA nor is there any NDA. Easy if you send UDP with checksums off or raw ethernet frames. Receiving party will of course need to ignore the last 4 bytes needed to make the CRC computation correct. Would be interesting if anyone managed to do this with TCP. If it's even possible to get both TCP and ethernet frame FEC match in real time and ideally somehow even mask the data from the recipient. Probably not possible, but... who knows.