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yeah but how many nm are left? There's a phsyical limit to transistor size!
by geogra4 7y ago
yeah but how many nm are left? There's a phsyical limit to transistor size!
- ivalm 7y agoThere is a lot of density that can be increased. The node size doesn't represent transistor size, not even the gate size.
- vasili111 7y agoWhat is the theoretical limit? I mean there should be end.
- umvi 7y agoWell, the diameter of a silicon atom is 0.2nm, so I would guess it's at least that with silicon-based computers.
- londons_explore 7y agoNot necessaraly. The node size represents the equivalent 'gate' size of a standard transistor with similar performance characteristics. By using better transistor designs, you can make the effective gate size much smaller than the actual gate size.
- 6nf 7y agoYou can't make features smaller than one atom though, and silicon atoms in a crystal matrix are about 0.5nm apart.
- pas 7y agoThe limit of information density is known as the Bekenstein bound. https://en.m.wikipedia.org/wiki/Bekenstein_bound https://en.m.wikipedia.org/wiki/Bekenstein_bound It is derived through quantum mechanics and via the Plank constants and black hole physics. Basically any more information squeezed together would turn into a black hole. Though ordinary (non quantum) thermodynamics limits information density well before this bound. As to what happens in the next decades with the good old Silicon stuff. Well, nobody knows just yet, but 3nm is what anyone realistically talks about, and just sci-fi tech after that.
- ivalm 7y agoCurrent density is ~100M (1E8) transistors/mm^2, Assuming transistors with a side of ~10 atoms (and bond length 0.5nm) that means we could get ~4E12 transistors/mm^2. This is almost certainly over optimistic but still it shows that we are orders of magnitude away from limits due to "atomic nature" of matter.
- ComputerGuru 7y agoI think you first need to switch to transistors/nm^3 rather than thinking only in 2d.
- ivalm 7y agoRight now these are planar devices. If you stack you can get orders of magnitude more. That's why you can get absurd memory capacities in things like nitrogen defect diamonds [0]. [0] https://advances.sciencemag.org/content/2/10/e1600911.full https://advances.sciencemag.org/content/2/10/e1600911.full
- sixplusone 7y agowouldn't that become a heat dissipation issue?
- ivalm 7y agoIf you need to move charge then you get nasty joule heating, but if you only move spin density then this causes almost no heating (that's the promise of spintronics)
- katuskoti 7y agoRemember the node size is more of a marketing term than anything now, and doesn't represent any actual dimension of the silicon.
- vbezhenar 7y agoI've heard about TSMC working on so-called "3nm", so while I don't know whether it approaches physical limits (those nanometers are just marketing speak after all), it's certain that we have another 10-15 years of progress ahead of us.
- 6nf 7y ago5 left
- gameswithgo 7y ago7 -> 7+/P -> 5 -> 5+/P -> 3 are all in the works already and that's just TMSC
- garmaine 7y agoThose aren’t forgone conclusions. That’s just guesswork on a whiteboard roadmap. At 10nm we are already at a stage where quantum effects start to dominate, and it’s not clear how much further these classical effects can scale. 7nm was “a process too far” for Intel, and it is a bit of a miracle that TSMC managed to pull it off.
- rrss 7y agoArguably, everything about a mosfet is a quantum effect. But anyway, undesirable quantum effects have been problematic for almost a decade, and were overcome with a variety of techniques (inc FinFET).
- kristofferR 7y ago5nm isn't just on a whiteboard, it's in risk production already at TSMC. Volume production is slated for Q1 2020, less than a year away, and TSMC tend to be accurate with their estimates.
- MegaButts 7y agoI hope you're right, but it's hard to imagine they aren't going to hit an unexpected wall at some point. The question is where is the wall? Basically you can never predict and unknown unknown.
- ksec 7y ago>I hope you're right, 5nm started risk production were direct from TSMC report. They are expecting even faster ramp than 7nm. And TSMC has a history of being very conservative. Their approach has been iteration rather than a leap like Intel did. And you can bet it will arrive on scheduled for next year's Apple iPhone. There are roadmap, tools, technique for 3nm ( As explained in the Article ) and even 2nm. So none of these are pipe dreams. As long as these customers can keep paying top dollar to be on leading node, TSMC seems to have no problem with innovating. The question is when will these clients slow down and stop paying every year because leading node is too expensive. Basically the cost of designing leading node is doubling every two year. So we are seeing something like the inverse of Moore's Law.
- baybal2 7y ago> There's a phsyical limit to transistor size! The size of transistors themselves were not changing much during last few node transition, what shrunk was the space and wiring in between of them.