>The compiler also does not necessarily know instruction latencies since they change from one CPU to the next. The instruction latencies are actually all docum

>The compiler also does not necessarily know instruction latencies since they change from one CPU to the next. The instruction latencies are actually all documented and modern compiler do take care when generating assembly code to optimize the output a bit to not stall the pipeline too often. I don't see how compilers, which have greatly improved since Itanium, shouldn't be able to tell when a load is best issued and be able to keep the pipelines full. >None of this is true. Prefetching looks at access patterns and pulls down sections of memory before they are accessed. That pretty much sounds like an optimization to caching for me. Granted, it's not precisely a caching algorithm but it's more of a cache predictor, but cache in the end. Compiler know best how to order instructions to ensure that loads happen when best needed and sufficiently beforehand that the data arrives in time without having to stall any part of the pipeline. The CPU solves it at runtime, why can't the compiler do it at compiletime when all the same information is available?