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How is loading a value from memory when an appropriate opcode comes in a dynamic property? Mill seems to be doing fine with their compiler and since Itanium com
by zaarn 7y ago
How is loading a value from memory when an appropriate opcode comes in a dynamic property? Mill seems to be doing fine with their compiler and since Itanium compilers have gotten a lot smarter.
- gpderetta 7y agoWhether a load is fulfilled from L1, L2, L3 or main memory is a dynamic property of the program and very hard to predict statically. Aliasing is also a dynamic property, but read ahead hardware should be able to handle it (but failure might stall the whole pipeline). Saying that Mill doing is fine might be tiny bit optimistic seening that the whole thing is still vaporware. Do they have a working compiler now?
- zaarn 7y agoAtleast judging from the latest posts on their forums, they have a working C compiler and are working on a C++ compiler to get a basic kernel for test harnesses running. I don't see why it matters to a deferred load being issued if the data is in L1, L2 or L3. The compiler emits a load, the caching hardware handles the rest, once the load arrives the pipeline unstalls. The compiler can atleast assume a L1 cache latency and then put some cycles between the load and execution. The earlier you can issue the load the better, if too early you might ruin it if you get preempted. Either way, it should not be hard to solve in VLIW.