Beyond approx 32 cores, cache coherent architectures don't scale. Intel faces enormous pressure to find consumer applications for message passing chip architect

Beyond approx 32 cores, cache coherent architectures don't scale. Intel faces enormous pressure to find consumer applications for message passing chip architectures otherwise the post 32 cores chips will be low volume products. Intel has been working very hard to find collaborators with application concepts for this era. Having this product permitts Intel to give them hardware rather that just FPGA simulators