4 ms·

Indeed, but that just means RISC-V designers have pursued the "less instructions" goal for its own sake. Having less instructions is not inherently beneficial.

Indeed, but that just means RISC-V designers have pursued the "less instructions" goal for its own sake. Having less instructions is not inherently beneficial. It can actually be detrimental: common operations require more instructions. https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d9982f7618ef68 https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d99...

nickik 7y ago
The RISC-V designers disagree. A number of typical patterns can be optimized easly by macro-op fusion in higher performance cores. The benfit is a decoder that has an incredibly small size, minimizing minimal core for RISC-V. Also RISC-V preferes less in in the core spec because if you have application that really needs something there will be standard extentions to add it.
- floatboth 7y ago
  > minimizing minimal core for RISC-V Again: why should I care about that? As a user, I care about big desktop-class cores, not academic minimal cores that fit on FPGAs. Small decoder is not a benefit for real world usage. > there will be standard extentions to add it That is, there will be fragmentation.
  - nickik 7y ago
    > Again: why should I care about that? Have you considered that the world doesn't revolve around you? You are infact wrong, many 'real world' uses like how small these cores can be. And given that many SoC now have lots and lots of small cores in them, having those cores be as small as possible is beneficial. > That is, there will be fragmentation. Yes. There will be fragmentation because an industry that is so broad, in terms of minimal soft cores to massive HPC systems, so having a true one-size-fits-all would have been doomed from the beginning and was never a viable design goal. RISC-V is design to approch the problem of a universal open-source ISA. It knows that avoiding fragmentation is impossible and thus they tried to build something that makes fragmentation managable both in terms of the organisation of the standard and in terms of the tools.

nickik 7y ago

The RISC-V designers disagree. A number of typical patterns can be optimized easly by macro-op fusion in higher performance cores. The benfit is a decoder that has an incredibly small size, minimizing minimal core for RISC-V. Also RISC-V preferes less in in the core spec because if you have application that really needs something there will be standard extentions to add it.

floatboth 7y ago
> minimizing minimal core for RISC-V Again: why should I care about that? As a user, I care about big desktop-class cores, not academic minimal cores that fit on FPGAs. Small decoder is not a benefit for real world usage. > there will be standard extentions to add it That is, there will be fragmentation.
- nickik 7y ago
  > Again: why should I care about that? Have you considered that the world doesn't revolve around you? You are infact wrong, many 'real world' uses like how small these cores can be. And given that many SoC now have lots and lots of small cores in them, having those cores be as small as possible is beneficial. > That is, there will be fragmentation. Yes. There will be fragmentation because an industry that is so broad, in terms of minimal soft cores to massive HPC systems, so having a true one-size-fits-all would have been doomed from the beginning and was never a viable design goal. RISC-V is design to approch the problem of a universal open-source ISA. It knows that avoiding fragmentation is impossible and thus they tried to build something that makes fragmentation managable both in terms of the organisation of the standard and in terms of the tools.