3 ms·
The chip is (in theory) very interesting to work with, but in practice it suffers a lot due to lack of cache control. Since the L2 cache is writeback (instead o
by merijnv 16y ago
The chip is (in theory) very interesting to work with, but in practice it suffers a lot due to lack of cache control. Since the L2 cache is writeback (instead of write-through) and because there is no cache flush instruction you are forced to manually flush your cache by reading from memory...
- jws 16y agoI think that is the point. If people are willing to program in this paradigm (message passing), then 1000+ core chips are possible. I think the question becomes: For problems decomposed into a message passing solution, is a 15x speedup for on die message passing a win at the 1000 core scale? Or another way around, for the scale problems that work at 1000 cores, is the message passing overhead is negligible and you can just as well stick them on separate dies/modules/blades/racks.
- merijnv 16y agoI agree that no cache coherency is the entire point of the chip, but the lack of manual control over things like flushing the cache is entirely unrelated to cache coherency and a significant issue in some of the things we've been trying to do on the chip.