3 ms·
> Many CISC machines (eg Intel's) are CISC in name only. The instructions are translated to micro-ops in the hardware. The micro-ops and the hardware itself, is
by adwn 7y ago
> Many CISC machines (eg Intel's) are CISC in name only. The instructions are translated to micro-ops in the hardware. The micro-ops and the hardware itself, is RISC.
This is an oft-repeated but incorrect statement. Modern x86 CPUs perform macro-op fusion and micro-op fusion. As an example of the former, a comparison and a jump instruction can be fused into a single micro-op [1], which is decidedly non-RISC. As for the latter, some micro-ops perform a load from memory and an arithmetic operation with the retrieved value – also very non-RISCy.
Modern x86 CPUs are CISC above and below the surface.
[1] https://en.wikichip.org/wiki/macro-operation_fusion#x86 https://en.wikichip.org/wiki/macro-operation_fusion#x86
- monocasa 7y agoYeah, vertical microcode always looked pretty RISCy if you're not used to it. And FWIW, I've heard that there's two distinct uOp formats inside a.single core these days for quite a few of the uArchs. There's the frontends view which is concerned with amortizing decode costs (so wide fixed purpose instructions, that other wise look pretty CISC), and the backend's uOps that's concerned with work scheduled on functional units. A lot of the fusion happens on the front end, and a lot of the cracking happens on the backend, and the frotbejd tends to be two address, and the backend three address. So like a frontend's and rax, [rbx, addr] is something like ld_agu t0, rbx, addr ld t1, t0 and rax, rax, t1 on the backend.
- CalChris 7y agoI'd add that horizontal microprogramming well predates RISC. x86 μops are wide.