CISC CPUs also take multiple instructions and combine them into larger uOPs through macro-op fusion. But whether or not the CPU's uOPs are RISC are not isn't r

CISC CPUs also take multiple instructions and combine them into larger uOPs through macro-op fusion. But whether or not the CPU's uOPs are RISC are not isn't really relevant here. The article is talking about pressure on things like L1. The argument is that CISC becomes almost a form of compression. If the CPU internally splits it into multiple uOPs that's fine - you still got the L1 savings, and those uOPs can potentially be more specialized. The CPU doesn't need to look ahead to see if the intermediate calculation is kept or anything like that. As in, it's overall more efficient to take a macro op and split it than take micro ops directly.