4 ms·

> The problem is that a modern CPU is so fast that just accessing the L1 cache takes anywhere from 3-5 cycles. Access to RAM on a MOS 6502 is about 2-6 cycles,

by leoc 7y ago

> The problem is that a modern CPU is so fast that just accessing the L1 cache takes anywhere from 3-5 cycles. Access to RAM on a MOS 6502 is about 2-6 cycles, isn't it? The total amount of RAM in a 6502 system is usually roughly the size of a modern L1 cache as well. It would be interesting if you could just program with an L1 exposed and structured as a main memory rather than a cache ...

AtlasBarfed 7y ago
With the embarrassment of riches in silicon real estate, I'm surprised there aren't SoC chips with a hundred or more megs of on-chip RAM. If we have room for 32 cores, then there have to be applications for 8 cores and RAM on-chip. My old 486 from the early 90's HDD almost fits in modern L3 cache.
- janoc 7y ago
  That RAM costs both in terms of space and power/heat. Especially high-speed cache RAM. That would make the SoCs huge and expensive for no particularly good reasons. Also large caches need a lot of logic to ensure coherency between multiple cores - with a small cache the probability of conflict isn't that big, so you can afford to keep it simple. With a huge cache such conflicts between cores would be pretty much assured and you would have to dedicate a lot of silicon just for managing access.
- floatboth 7y ago
  Zen 2 has 16MB L3 per CCX, so e.g. 70MB total on the 12-core. Not a hundred, but quite a lot. It's Huge.
toast0 7y ago
> Access to RAM on a MOS 6502 is about 2-6 cycles, isn't it? The 6502 accesses the memory bus every cycle, although for some cycles of some instructions, the value read isn't used; as a result, RAM and ROM in a 6502 system needs to be fast relative to the CPU. Perhaps you're thinking about the instruction latencies, which are 2-6 cycles, depending on the instruction and the addressing mode and what not. (BRK (0x00) aka software interrupt is 7, though)
rwallace 7y ago
> Access to RAM on a MOS 6502 is about 2-6 cycles, isn't it? One cycle. Of course, the cycles are a lot slower. > It would be interesting if you could just program with an L1 exposed and structured as a main memory rather than a cache ... The Cell processor, used in the PlayStation 3, provided something like that. What happened in practice was that programmers trying to get code working soon enough to be useful, just ended up leaving most of the theoretical performance on the table, which is why the next generation of consoles scrapped the idea in favor of a conventional x64 CPU.
temac 7y ago
> It would be interesting if you could just program with an L1 exposed and structured as a main memory rather than a cache ... During the boot of the computer, you can. At least you could a few years ago, I'm not sure about brand new processors. Anyway, the boot was (and maybe still is) done in multiple phases and at first the RAM is not available. So at first the code only uses registers. But this is extremely limiting (I'm not sure there are even compilers capable to emit such code, so you have to write that shit in assembly language). So one of the first thing to do, even before you have the memory controller programmed and calibrated, is that you flip a bunch of model specific registers, run a tiny loop to touch a range of addresses, and update the MSRs again to prevent the cache lines from being evicted, and BOOM! You go into the Cache-As-Ram mode. Later you will initialize the memory controller, and leave Cache-As-Ram. I'm not sure if you can hard-limit to L1 though (well obviously you can if you restrict to a small enough range). Probably L1+L2 is used most of the time? Not really sure... Maybe you can take a look at coreboot and actually program the application you want in there instead of under a traditional OS. Seems fun :P

by leoc 7y ago

AtlasBarfed 7y ago

With the embarrassment of riches in silicon real estate, I'm surprised there aren't SoC chips with a hundred or more megs of on-chip RAM. If we have room for 32 cores, then there have to be applications for 8 cores and RAM on-chip. My old 486 from the early 90's HDD almost fits in modern L3 cache.

janoc 7y ago
That RAM costs both in terms of space and power/heat. Especially high-speed cache RAM. That would make the SoCs huge and expensive for no particularly good reasons. Also large caches need a lot of logic to ensure coherency between multiple cores - with a small cache the probability of conflict isn't that big, so you can afford to keep it simple. With a huge cache such conflicts between cores would be pretty much assured and you would have to dedicate a lot of silicon just for managing access.
floatboth 7y ago
Zen 2 has 16MB L3 per CCX, so e.g. 70MB total on the 12-core. Not a hundred, but quite a lot. It's Huge.

toast0 7y ago

> Access to RAM on a MOS 6502 is about 2-6 cycles, isn't it? The 6502 accesses the memory bus every cycle, although for some cycles of some instructions, the value read isn't used; as a result, RAM and ROM in a 6502 system needs to be fast relative to the CPU. Perhaps you're thinking about the instruction latencies, which are 2-6 cycles, depending on the instruction and the addressing mode and what not. (BRK (0x00) aka software interrupt is 7, though)

rwallace 7y ago

> Access to RAM on a MOS 6502 is about 2-6 cycles, isn't it? One cycle. Of course, the cycles are a lot slower. > It would be interesting if you could just program with an L1 exposed and structured as a main memory rather than a cache ... The Cell processor, used in the PlayStation 3, provided something like that. What happened in practice was that programmers trying to get code working soon enough to be useful, just ended up leaving most of the theoretical performance on the table, which is why the next generation of consoles scrapped the idea in favor of a conventional x64 CPU.

temac 7y ago

> It would be interesting if you could just program with an L1 exposed and structured as a main memory rather than a cache ... During the boot of the computer, you can. At least you could a few years ago, I'm not sure about brand new processors. Anyway, the boot was (and maybe still is) done in multiple phases and at first the RAM is not available. So at first the code only uses registers. But this is extremely limiting (I'm not sure there are even compilers capable to emit such code, so you have to write that shit in assembly language). So one of the first thing to do, even before you have the memory controller programmed and calibrated, is that you flip a bunch of model specific registers, run a tiny loop to touch a range of addresses, and update the MSRs again to prevent the cache lines from being evicted, and BOOM! You go into the Cache-As-Ram mode. Later you will initialize the memory controller, and leave Cache-As-Ram. I'm not sure if you can hard-limit to L1 though (well obviously you can if you restrict to a small enough range). Probably L1+L2 is used most of the time? Not really sure... Maybe you can take a look at coreboot and actually program the application you want in there instead of under a traditional OS. Seems fun :P