RISC-V from the beginning was designed to work perfectly fine with vector processing. The lab that developed RISC-V made RISC-V to have an architecture that wou

RISC-V from the beginning was designed to work perfectly fine with vector processing. The lab that developed RISC-V made RISC-V to have an architecture that would allow them to use different vector units and experiment with different vector architectures. The Berkley Parallel Comouting Lab is where the worked on RISC-V. The RISC-V V extention is the result of this work and exploration into parallel architecture. RISC-V was to be modular and the V extention is just as much part of RISC-V as the F extention.