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Reminder: all current, performant CISC CPUs just internally (in microcode) compile instructions down to smaller uOPs, which are then executed by a RISC-like cor
by jasonhansel 7y ago
Reminder: all current, performant CISC CPUs just internally (in microcode) compile instructions down to smaller uOPs, which are then executed by a RISC-like core. CISC chips are just RISC chips with fancier interfaces.
- kllrnohj 7y agoCISC CPUs also take multiple instructions and combine them into larger uOPs through macro-op fusion. But whether or not the CPU's uOPs are RISC are not isn't really relevant here. The article is talking about pressure on things like L1. The argument is that CISC becomes almost a form of compression. If the CPU internally splits it into multiple uOPs that's fine - you still got the L1 savings, and those uOPs can potentially be more specialized. The CPU doesn't need to look ahead to see if the intermediate calculation is kept or anything like that. As in, it's overall more efficient to take a macro op and split it than take micro ops directly.
- astrodust 7y agoIt used to be an architectural distinction but now it's just marketing, if even that much. When PowerPC started adding complex vector instructions (AltiVec) and the Pentium turned x86 into a RISC core with translation layer around it you knew the distinction was pretty much dead.