I was under the impression that CISC processors have utiliized instruction pipelining for a long time already. Here's what Wikipedia has to say about it: The

I was under the impression that CISC processors have utiliized instruction pipelining for a long time already. Here's what Wikipedia has to say about it: The terms CISC and RISC have become less meaningful with the continued evolution of both CISC and RISC designs and implementations. The first highly (or tightly) pipelined x86 implementations, the 486 designs from Intel, AMD, Cyrix, and IBM, supported every instruction that their predecessors did, but achieved maximum efficiency only on a fairly simple x86 subset that was only a little more than a typical RISC instruction set (i.e. without typical RISC load-store limitations). The Intel P5 Pentium generation was a superscalar version of these principles. However, modern x86 processors also (typically) decode and split instructions into dynamic sequences of internally buffered micro-operations, which not only helps execute a larger subset of instructions in a pipelined (overlapping) fashion, but also facilitates more advanced extraction of parallelism out of the code stream, for even higher performance.[1] And Intel has an article on how instruction pipelining is done which covers CISC designs as well.[2] 1. https://en.wikipedia.org/wiki/Complex_instruction_set_computer#CISC_and_RISC_terms https://en.wikipedia.org/wiki/Complex_instruction_set_comput... 2. https://techdecoded.intel.io/resources/understanding-the-instruction-pipeline/ https://techdecoded.intel.io/resources/understanding-the-ins...