3 ms·
Although the micro-operations are dispatched to many parallel execution units, so it's really better described as VLIW.
by gnode 7y ago
Although the micro-operations are dispatched to many parallel execution units, so it's really better described as VLIW.
- jasonwatkinspdx 7y agoNo, that's just superscalar. The defining feature of VLIW is that the the compiler schedules the dispatch.
- Erwin 7y agoThe ports/schedulers have quite different capabilities however: https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Scheduler_Ports_.26_Execution_Units https://en.wikichip.org/wiki/intel/microarchitectures/skylak... Using the Intel Vtune tools you can see how each port is utilized, so you could in theory change your code to mix instructions for best utilization beyond what reordering the CPU can do itself, so I can see some analogy with building a VLIW instruction group. There's a crazy amount of performance counters you can look at (the perf tool can do that too, but just try running "perf list" to view available counters).