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What about SGI Onyx https://m.slashdot.org/story/12659 https://m.slashdot.org/story/12659 Seems that mips was scalable back then There was a story headline a

by ohiovr 7y ago

What about SGI Onyx https://m.slashdot.org/story/12659 https://m.slashdot.org/story/12659 Seems that mips was scalable back then There was a story headline about a 16 core RISC V just the other day

bestouff 7y ago
Here it is: https://www.theregister.co.uk/2019/07/27/alibaba_risc_v_chip/ https://www.theregister.co.uk/2019/07/27/alibaba_risc_v_chip...
ajross 7y ago
That's not the scalability the article is talking about. It's about instructions per cycle, and the fact that this gets pretty firmly capped by the bandwidth and latencies of the cache hierarchy, so even with ~6 parallel execution units it's pretty rare to be able to fill more than 2 of them in a cycle. And this is true, but it has absolutely nothing to do with instruction architecture. The rest of the article is talking about how VLIW "solves" this problem, which is does not. Given an existing parallelizable problem, a VLIW architecture can encode the operations a little more efficiently, and the decode hardware required to interpret the instructions can be a lot simpler. But that's as far as it goes. If you have a classic CPU which can decode 4 instructions in a cycle, then it can decode 4 instructions in a cycle and VLIW isn't going to improve that except by reducing die area. VLIW also forces compilers to make a choice between crazy specificity to specific hardware architectures, or an insanely complicated ISA with a batching scheme a-la Itanium. This is largely why it failed, not that "compilers weren't smart enough". There's nothing wrong with RISC. Or classic CISC. Even VLIW isn't bad, really. The sad truth is that ISAs just don't matter. They're a tiny bit of die area and a few pipeline stages in much larger machines, and instruction decode is largely a solved problem. Programmers just like to yell about ISA because that's what software touches, and we understand that part.
- gpderetta 7y ago
  Amen.
erk__ 7y ago
And POWER is also pretty scaleable, else I guess that they would use something else for supercomputers.

by ohiovr 7y ago

What about SGI Onyx https://m.slashdot.org/story/12659 https://m.slashdot.org/story/12659 Seems that mips was scalable back then There was a story headline about a 16 core RISC V just the other day

bestouff 7y ago

Here it is: https://www.theregister.co.uk/2019/07/27/alibaba_risc_v_chip/ https://www.theregister.co.uk/2019/07/27/alibaba_risc_v_chip...

ajross 7y ago

That's not the scalability the article is talking about. It's about instructions per cycle, and the fact that this gets pretty firmly capped by the bandwidth and latencies of the cache hierarchy, so even with ~6 parallel execution units it's pretty rare to be able to fill more than 2 of them in a cycle. And this is true, but it has absolutely nothing to do with instruction architecture. The rest of the article is talking about how VLIW "solves" this problem, which is does not. Given an existing parallelizable problem, a VLIW architecture can encode the operations a little more efficiently, and the decode hardware required to interpret the instructions can be a lot simpler. But that's as far as it goes. If you have a classic CPU which can decode 4 instructions in a cycle, then it can decode 4 instructions in a cycle and VLIW isn't going to improve that except by reducing die area. VLIW also forces compilers to make a choice between crazy specificity to specific hardware architectures, or an insanely complicated ISA with a batching scheme a-la Itanium. This is largely why it failed, not that "compilers weren't smart enough". There's nothing wrong with RISC. Or classic CISC. Even VLIW isn't bad, really. The sad truth is that ISAs just don't matter. They're a tiny bit of die area and a few pipeline stages in much larger machines, and instruction decode is largely a solved problem. Programmers just like to yell about ISA because that's what software touches, and we understand that part.

gpderetta 7y ago
Amen.

erk__ 7y ago

And POWER is also pretty scaleable, else I guess that they would use something else for supercomputers.