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All you see is 8 server racks with colored network cables, switches and power supplies. The TPU ASICs themselves make up just a tiny part of this datacenter, yo
by morphle 7y ago
All you see is 8 server racks with colored network cables, switches and power supplies. The TPU ASICs themselves make up just a tiny part of this datacenter, you also have the printed circuit boards, cooling fins, 8x48 metal boxes, power and network cables, DC/DC or AC/DC converters at the bottom, fans or water tubes for cooling and airgaps.
My startup is trying to develop wafer scale integration where you collapse 2 racks of the network, metal boxes, power and cooling into a 300mm wafer immersed a 100 mm x 400mm box with a few fibers and three power cables coming out. That can save around 900% of the capital cost and orders of magnitude of power (especially if you put the box in a building where the waste heat is not wasted but used to heat water for showering and space heating).
As it is now, these datacenter customers and hyperscalers don't seem to care about the enormous waste and cost of paying for inefficient hardware. Considering the enormous cost and carbon emmission savings a wafer scale integration would bring (and the competitive advantage), you would be suprised how hard it is to get funding from them to develop it.
I suspect is also the main reason they don't care to publish normalized benchmarks for $/performance/joule, as it would demonstrate how wasteful it all is.
- rrss 7y ago> would be suprised how hard it is to get funding from them to develop it. That's probably because there has been no evidence that wafer scale integration can actually work.
- morphle 7y agoI agree there is no complete evidence of a full WSI yet. There are several recent papers on Wafer Scale Integration (WSI) and some WSI built (large sensors) with reasonable yields. There are many papers on partial problem solutions that, if combined in one project would yield a full working WSI with existing 7nm standard CMOS process. There are silicon interconnect fabric (SiIF) which is one step removed from a full WSI. There are many commercial chips 1/70th the size of a WSI already and some unpublished WSI results.