4 ms·
It looks like an unreliable modification. PCIe is surprisingly robust at short lengths. For example, [NanoPi_M4] has two lanes of PCIe coming to the daughterbo
by kees99 7y ago
It looks like an unreliable modification.
PCIe is surprisingly robust at short lengths. For example, [NanoPi_M4] has two lanes of PCIe coming to the daughterboards via old-school 0.1" connector. Something that many electrical engineers would cringe at, and yet - it works rather reliably.
[NanoPi_M4] http://wiki.friendlyarm.com/wiki/index.php/NanoPi_M4#Layout http://wiki.friendlyarm.com/wiki/index.php/NanoPi_M4#Layout
- userbinator 7y agoExactly, the PCIe reference clock is "only" 100MHz. USB 2.0 runs at 480MHz and motherboards have used 0.1" headers for them since the beginning.
- LIV2 7y agoWhile the ref clock is only 100MHz the data rate of PCI Express is much higher, it's a serial bus pushing multiple gigabits a second https://electronics.stackexchange.com/a/259002 https://electronics.stackexchange.com/a/259002
- baybal2 7y agoYes, the theoretical maximum (nyquist freq) of PCIe 4 is 8ghz
- Kirby64 7y agoThe Pi4 isn't PCIe Gen 4, though. It's only PCIe Gen 2. Max speed of PCIe Gen 2 is 5GT/s, which equates to the same speed as standard USB3.0/USB3.1 Gen1/whatever its called nowadays.
- baybal2 7y agoNyqist frequency of 2Ghz for PCIe 2 (slightly less in practice due to line code) is still nothing to sneeze at.
- Kirby64 7y ago2.5 GHz, actually. Obviously there's limitations and you have to be careful, but it's not too crazy to think you could use a piece of USB3 cabling to do this. Requires some pretty precise soldering skills though.