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Can anybody explain the poor memory latency numbers? Is this due to the new L3 and chiplet design or is it from the larger L3? Intel chunks their LL cache out t
by jnordwick 7y ago
Can anybody explain the poor memory latency numbers? Is this due to the new L3 and chiplet design or is it from the larger L3? Intel chunks their LL cache out too, so I wasnt expecting such a big difference.
Also AMD got stomped on the system performance testing (those tests seem like they might be difficult to unpack into individual reasons given their breadth). Why would that be the case.
And WOW. Any vectorised workloads written for AVX-512... Besides the larger operand sizes, the instruction set changed seem to matter hugely. I did a small not using avx512 too effectively scan hash table for the keys, and it made a huge difference too.
Still considering the top Ryzen chip for a sorely need new desktop, but I don't play games so it would mostly be a cost thing.
- HeWhoLurksLate 7y agoIf I understand correctly, the higher memory latency is a between-chiplet problem for the most part, with the highest latencies being between CCX's. If you don't game, I see absolutely no reason not to buy Ryzen, but you might not need to buy an X570 mobo.
- jnordwick 7y agoIntel's L3 is sharded out into 2mb chunks on a ring bus too so I would have expected more comparable numbers. Is Intel's QPI link and cache coherency implemention that much better?