I love that the input is using inverted logic due to the voltage translation needed, but the code and comments don't mention this. To me it looks like an obvio

I love that the input is using inverted logic due to the voltage translation needed, but the code and comments don't mention this. To me it looks like an obvious bug and first glance, since the CAPITALIZED sigal states don't match between code and comments. Glad I read the article first. :)