3 ms·
Pity it is implemented in Bluespec Verilog for which the only viable toolchain is still closed source software. Some unsupported since 2013 toy compilers exist.
by peter_beck 7y ago
Pity it is implemented in Bluespec Verilog for which the only viable toolchain is still closed source software.
Some unsupported since 2013 toy compilers exist.
Looks like the company behind the Bluespec pivoted to RISC-V implementation.
Bluespec HDL has seen its limelight in 2012 and died due to it being closed source with pricing similarly excessive as other HDL tools.
I remember being excited about the possibilities of a new, paradigm shifting HDL.
Sadly, now it is a fizzled remainder of how to run the good tech into the ground by keeping it closed.
- snaky 7y ago> Fe-Si is a simplified version of Bluespec, an HDL based on a notion of guarded atomic actions. Fe-Si is defined as a dependently typed deep embedding in Coq. The target language of the compiler corresponds to a synthesisable subset of Verilog or VHDL. A key aspect of our approach is that input programs to the compiler can be defined and proved correct inside Coq. Then, we use extraction and a Verilog back-end (written in OCaml) to get a certified version of a hardware design. http://adam.chlipala.net/papers/FesiCAV13/ http://adam.chlipala.net/papers/FesiCAV13/ https://github.com/braibant/Synthesis https://github.com/braibant/Synthesis
- 0815test 7y ago> I remember being excited about the possibilities of a new, paradigm shifting HDL. 2012 was a long time ago. There are plenty of RISC-V core implementations using Chisel and other "paradigm shifting" HDL tools.
- snaky 7y agoLava, Esterel, what else?