2 ms·
OK, but it's not just the clock rate that enters into the decision, one must also consider the rise-time of the edges. If you're using, for example, a fast log
by crispyambulance 7y ago
OK, but it's not just the clock rate that enters into the decision, one must also consider the rise-time of the edges.
If you're using, for example, a fast logic family like LVC, fast edges on badly routed traces can radiate and interfere with other parts of the circuit, even if you're dealing with "low" clock rates or simple un-clocked logic.
- Junk_Collector 7y agoYes, the rule of thumb for low frequency square wave clocks (a few GHz or less) is that your trace, routing, and connectors should all support up to the 5th harmonic, or 5 times the clock frequency. At higher frequencies the 5th harmonic is to high to realistically achieve, and you start to see reliance on sine wave clocks or heavy use of equalization to remove clock distortion from the trace. This applies for digital buses as well. If anyone is curious about how traces impact data throughput, I highly recommend they look up eye diagrams.