Mostly people don't make fault tolerant hardware - instead we do die level tests (first on bare dies and then in depth on packaged ones) and toss the bad dies.

Mostly people don't make fault tolerant hardware - instead we do die level tests (first on bare dies and then in depth on packaged ones) and toss the bad dies. However we're talking here about building 3D stacked devices instead, to get speed we're going to build cubic CPUs (to reduce speed of light delays), not piles of single layer square CPUs, maybe 100 layers deep - certainly we can disable bad CPUs but that still means we're getting an error rate at P^100