3 ms·
This has arguably already been appearing on the graphics side with stacked memory, but now Intel is getting serious about this approach: https://www.theverge.co
by eloff 7y ago
This has arguably already been appearing on the graphics side with stacked memory, but now Intel is getting serious about this approach: https://www.theverge.com/2019/1/7/18173001/intel-lakefield-foveros-3d-chip-stacking-soc-design-ces-2019 https://www.theverge.com/2019/1/7/18173001/intel-lakefield-f...
A big problem is heat. But stacked designs produce less heat overall, just in a smaller area. That can actually make heat dissipation more centralized and more efficient (due to higher thermal gradient) so I think it's a solvable problem.
- Retra 7y agoI think if you can properly do a fully 3D circuit, you will probably also free up a lot of space to interleave heat pipes within.
- undersuit 7y agoMake Peltier cooling wires at the same transistor size throughout the chip to cool the interior and dump all the heat on the outside. Peltier coolers are supposed to be inefficient, but when you need to cool the interior of a cube a few millimeters across you don't have many options.