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Moore's law is dead, but I don't think the story ends there. Now the incentives exist to explore alternatives to Silicon, which could yield many more years of b
by eloff 7y ago
Moore's law is dead, but I don't think the story ends there. Now the incentives exist to explore alternatives to Silicon, which could yield many more years of big process improvements. While Silicon was scaling so rapidly there was little point in investing in alternatives. The free lunch is over, but the stage is set for the next act of the microprocessor revolution.
- msla 7y agoI wonder if architectural diversity will increase even further than it has. It's already increased a bit in the microprocessor world with the rise of GPUs, but that "just" puts supercomputer-style vector processing in SBCs and laptops. It isn't as new of a concept as systolic arrays, for example; those can be fast even on slow hardware if you pick your problem right, just like how GPUs are only speed demons on certain tasks. Well, if we can't beat problems to death with increasing scalar speed, it might give us more incentives to design ever-more-specialized chips which solve specific problems extremely effectively even if they're comically useless for general-purpose computing.
- stcredzero 7y agoWell, if we can't beat problems to death with increasing scalar speed For those not immediately familiar with the terminology: "scalar" is Single Instructions, Single Data. https://en.wikipedia.org/wiki/Flynn%27s_taxonomy https://en.wikipedia.org/wiki/Flynn%27s_taxonomy
- Nuzzerino 7y agoRay Kurzweil has long predicted 3D computing chips would become a paradigm. I'm not talking about GPUs, but actually vertically stacked layers of transistors. https://www.kurzweilai.net/radical-new-vertically-integrated-3d-chip-design-combines-computing-and-data-storage https://www.kurzweilai.net/radical-new-vertically-integrated...
- eloff 7y agoThis has arguably already been appearing on the graphics side with stacked memory, but now Intel is getting serious about this approach: https://www.theverge.com/2019/1/7/18173001/intel-lakefield-foveros-3d-chip-stacking-soc-design-ces-2019 https://www.theverge.com/2019/1/7/18173001/intel-lakefield-f... A big problem is heat. But stacked designs produce less heat overall, just in a smaller area. That can actually make heat dissipation more centralized and more efficient (due to higher thermal gradient) so I think it's a solvable problem.
- Retra 7y agoI think if you can properly do a fully 3D circuit, you will probably also free up a lot of space to interleave heat pipes within.
- undersuit 7y agoMake Peltier cooling wires at the same transistor size throughout the chip to cool the interior and dump all the heat on the outside. Peltier coolers are supposed to be inefficient, but when you need to cool the interior of a cube a few millimeters across you don't have many options.
- tracker1 7y agoI think the issue there will be heat dissipation in general. IIRC, this was the plan for some of Intel's upcoming chips and is limiting the throughput frequencies as a result. This could mean more horizontal scaling, but limiting the frequencies to laptop/server levels. Though a lot of current games are more parallel, there's still a lot of gameplay on games that are optimized for single core frequency. I do agree, the longer term will lead to stacking, I'm just not sure how far off that is in realistic terms, and if the complexities may outweigh the benefits in a lot of use cases. The node shrinks are definitely slowing and have for a several years.