4 ms·
AFAIK yes. You start to run into problems because the area you're trying to make a transistor in might not contain one of the dopant atoms which determine the
by 01100011 7y ago
AFAIK yes. You start to run into problems because the area you're trying to make a transistor in might not contain one of the dopant atoms which determine the semiconductor type. I believe hot carrier injection becomes more of a problem as well. At some point you probably run into quantum effects as electrons just start tunneling where they're not supposed to.
On top of all that, the design rules become crazy at small dimensions. You can't just make a sharp bend in a wire because the high frequency component of the bend causes ringing in the interference pattern of the EUV laser.
* - I'm just a software guy with a BSEE... I'm curious what a semiconductor designer has to say about all this.
- brennanpeterson 7y agoYou end up with fully depleted devices to avoid dopant effects. And tunneling loss is already an issue, and is mitigated with better work function metal design. Sharp bends don't happen because they cause large fields which in turn cause dielectric breakdown. Most critical metal layers are oriented in a single direction. 2D printing with EUV isn't really an issue. There are three components which make the area of a cell that are used to infer the scaling. The fin pitch, the metal pith, and the cell height (track count). An older technology (22nm) might have a 9track, 40nm by 60nm size. 14nm would be 9T2842, 10 would be 7.5T2638, 7 would be 6.5T2638 with SDB, and 5 might be 5.5T2230 Numbers very approximate, but the key is that design compaction (which requires major physical integration changes) coupled with reduced key pitch shrink. The nice part is that you tend to get more design innovation, because you are no longer competing with shrink. And the relative cost of additional masks and layers is low.