4 ms·
If I understand it correctly, 3 nm is less than ten atoms. Cannot this make the technology much less reliable due to quantum effects and interference?
by js8 7y ago
If I understand it correctly, 3 nm is less than ten atoms. Cannot this make the technology much less reliable due to quantum effects and interference?
- kragen 7y agoIt's about 30 atoms, depending on the material. Silicon's covalent radius is 111 pm, so it's 27 silicon atoms. But the 3nm process node doesn't mean that all the features are 3nm wide; a lot of things are twice that wide in many processes. Sounds like 3nm is pretty weird, though, so all bets are off. IBM fabricated single-atom transistors that worked with adequate reliability back in the 1990s, IIRC. I don't know how bad the noise problem you allude to really is.
- Certhas 7y agoBut the covalent radius is not the crucial property here, the silicone lattice spacing is, and that's 0.5nm so a 2nm wide element is 4 atoms across.
- Certhas 7y agoCorrection: The lattice spacing gives the size of the fundamental building block of the lattice, which includes several atoms. The nearest neighbour distance in the lattice is 0.235 nm. Wikipedia has a nice picture of the lattice structure: https://en.wikipedia.org/wiki/Diamond_cubic#/media/File:Visualisation_diamond_cubic.svg https://en.wikipedia.org/wiki/Diamond_cubic#/media/File:Visu... Part 3 of the picture is a 3x3x3 block of elementary cells, for silicon this would be 1.63nm along each edge, so for a 2nm element you get a few more atoms in each direction.
- kragen 7y agoThank you both for the correction!
- deepnotderp 7y agoNode names stopped meaning anything a long time ago, it's not really 3nm, that's just the marketing name. Think 11 inch "Footlong" but more extreme. That being said, direct S/D tunneling is expected to become an issue at channel lengths of around 1nm, although anisotropic carrier mass can be used to delay this further.
- 01100011 7y agoAFAIK yes. You start to run into problems because the area you're trying to make a transistor in might not contain one of the dopant atoms which determine the semiconductor type. I believe hot carrier injection becomes more of a problem as well. At some point you probably run into quantum effects as electrons just start tunneling where they're not supposed to. On top of all that, the design rules become crazy at small dimensions. You can't just make a sharp bend in a wire because the high frequency component of the bend causes ringing in the interference pattern of the EUV laser. * - I'm just a software guy with a BSEE... I'm curious what a semiconductor designer has to say about all this.
- brennanpeterson 7y agoYou end up with fully depleted devices to avoid dopant effects. And tunneling loss is already an issue, and is mitigated with better work function metal design. Sharp bends don't happen because they cause large fields which in turn cause dielectric breakdown. Most critical metal layers are oriented in a single direction. 2D printing with EUV isn't really an issue. There are three components which make the area of a cell that are used to infer the scaling. The fin pitch, the metal pith, and the cell height (track count). An older technology (22nm) might have a 9track, 40nm by 60nm size. 14nm would be 9T2842, 10 would be 7.5T2638, 7 would be 6.5T2638 with SDB, and 5 might be 5.5T2230 Numbers very approximate, but the key is that design compaction (which requires major physical integration changes) coupled with reduced key pitch shrink. The nice part is that you tend to get more design innovation, because you are no longer competing with shrink. And the relative cost of additional masks and layers is low.
- deleted 7y ago[deleted]
- tfha 7y ago3nm node means feature sizes in the range of 20-30nm. Names don't mean so much anymore