Yes, but LLVM is not very suitable in general for FPGA/ASIC design. FIRRTL[1][2] looks much more complete and fit among various alternatives. [1] https://bar.e

Yes, but LLVM is not very suitable in general for FPGA/ASIC design. FIRRTL[1][2] looks much more complete and fit among various alternatives. [1] https://bar.eecs.berkeley.edu/projects/firrtl.html https://bar.eecs.berkeley.edu/projects/firrtl.html [2] https://github.com/freechipsproject/firrtl https://github.com/freechipsproject/firrtl