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> There is no synthesis engine for VHDL in it that I'm aware of. The answer is one simply Google search away: http://www.clifford.at/yosys/cmd_verific.html htt
by tverbeure 7y ago
> There is no synthesis engine for VHDL in it that I'm aware of.
The answer is one simply Google search away:
http://www.clifford.at/yosys/cmd_verific.html http://www.clifford.at/yosys/cmd_verific.html
The commercial version of Symbiyosys uses Verific to parse and elaborate designs. The Verific front-end supports Verilog, SystemVerilog and VHDL.
When it comes to formal verification, the Verific front-end and the Yosys Verific backend support a large set of the formal verification primitives of SystemVerilog. (See also the above link.)