I’m not quite sure I understand your discontent. You assert the author displays a “willful misunderstanding of the differences between FPGAs, GPUs, and ASICs.”

I’m not quite sure I understand your discontent. You assert the author displays a “willful misunderstanding of the differences between FPGAs, GPUs, and ASICs.” What differences did the author misrepresent? And is it fair to call it “willful”? From what I can tell, the ideas should be taken at a 10,00ft view: Verilog as an interface to (computational) FPGAs is not good enough because it’s inaccessible to domain scientists in other fields (where CUDA and similar are). The way I read the post was the author is framing a research question: “how do we design a new abstraction for FPGAs to do for them what we’ve done for GPUs?”