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This is a useless post: bunch of complaining about the author’s own ignorance of FPGA and computational fabrics, willful misunderstanding of the differences bet
by jgeada 7y ago
This is a useless post: bunch of complaining about the author’s own ignorance of FPGA and computational fabrics, willful misunderstanding of the differences between FPGAs, GPUs, ASICs, and lastly, not even an attempted proposal for a way forward past the author’s inabilities.
Why did I just waste time reading this crap?
- ninjacatex 7y agoI’m not quite sure I understand your discontent. You assert the author displays a “willful misunderstanding of the differences between FPGAs, GPUs, and ASICs.” What differences did the author misrepresent? And is it fair to call it “willful”? From what I can tell, the ideas should be taken at a 10,00ft view: Verilog as an interface to (computational) FPGAs is not good enough because it’s inaccessible to domain scientists in other fields (where CUDA and similar are). The way I read the post was the author is framing a research question: “how do we design a new abstraction for FPGAs to do for them what we’ve done for GPUs?”