If Verilog is your target, compile times will be too slow. This is better: "We describe a hybrid area estimation technique which uses template-level models an

If Verilog is your target, compile times will be too slow. This is better: "We describe a hybrid area estimation technique which uses template-level models and design-level artificial neural networks to account for effects from hardware place-and-route tools, including routing overheads, register and block RAM duplication, and LUT packing...We show that estimates average 4.8% error for logic resources, 6.1% error for runtimes, and are 279 to 6533 times faster than a commercial high-level synthesis tool." https://ieeexplore.ieee.org/document/7551387 https://ieeexplore.ieee.org/document/7551387 And based on this representation , they've built a high level language for FPGA accelerators, available to download: https://spatial-lang.org/ https://spatial-lang.org/