The general version of the thing you're describing is a 2d systolic array. Designs like this already map reasonably well to standard FPGAs. The problem with th

The general version of the thing you're describing is a 2d systolic array. Designs like this already map reasonably well to standard FPGAs. The problem with the 4:4 LUT you described above is that you almost always want the compute cell part of your design to have inputs and outputs that are wider than a single bit. For example, if you were designing an FIR filter as a systolic array, you might want one filter coefficient to come from the top of each cell, and your signal to pass through the cells from left to right. A realistic design might have a 16 bit signal and 10 bit coefficients. This would require 160 LUTs per cell just to size the signals correctly. You'd need a lot more in practice, because in addition to fitting your compute cell logic, state machine logic, and arithmetic logic, you also need to waste extra LUTs to route the arithmetic carry chains and state machine signals across this LUT grid. And even if you manage to do all that, you're still left with a bit-serial design that needs to be clocked an order of magnitude faster than a design with wider inter-cell transfer sizes to get similar performance. When you start thinking about ways to get around some of these limitations while keeping designs with high "spacial locality" efficient, you get something that looks a lot like a modern FPGA.