Readable version of the quoted paragraph: The problem with Verilog as an ISA is that it is too far removed from the hardware. The abstraction gap between RTL a

Readable version of the quoted paragraph: The problem with Verilog as an ISA is that it is too far removed from the hardware. The abstraction gap between RTL and FPGA hardware is enormous: it traditionally contains at least synthesis, technology mapping, and place & route—each of which is a complex, slow process. (Don't use code formatting for quotes.)