I agree with the first part of your comment but you lost me there: >Timing is important, placement is important, mapping is important. It's true, but Verilog

I agree with the first part of your comment but you lost me there: >Timing is important, placement is important, mapping is important. It's true, but Verilog doesn't usually expose that. You let the tool figure out the placement, routing and do the timing analysis. If you want to mess with that by yourself you usually have to use tool-specific methods to partition your design and do partial routings for instance. I don't think you're arguing otherwise but then I'm not sure what you're getting at. I don't directly do FPGA development myself but I do work with FPGA/ASIC developers (I do the software side of things) and boy I do not envy them. It makes me realize how lucky we are in the software world for GCC/LLVM and all the other open source tools we get to use. You don't have to use unstable, buggy, obscure programs that are effectively unusable for anything remotely advanced if you don't have a support contract with the vendor to help you figure out what to do when something is not working as intended.