Seems like the author is arguing that when FPGAs are used for "computation" and not for prototyping or replacing ASICs for low volume production, there should b

Seems like the author is arguing that when FPGAs are used for "computation" and not for prototyping or replacing ASICs for low volume production, there should be an ISA to abstract the gory details like in GPUs/CPUs, and Verilog is not an adequate abstraction in that regard because it's more like a programming language. Now, I may misinterpret the author's argument, but I don't understand the obsession over ISAs. It's a bit short sighted IMHO and, I agree with you, HDLs may not be elegant or pretty but they do their job just fine, ie. low level modeling at the primitive level. They are not programming languages. I also don't see how vendor locking fits with the rest of the narrative. Whatever intermediate abstraction the vendors offer (the author gives no examples which makes the post read more like a rant) it still won't expose the inner workings which (unlike CPUs/GPUs) are crucial for truly open FPGA development. Now should we strive for a better alternative, an evolution to FPGAs that benefit from an "ISA" type of abstraction? I'm not smart enough to visualize it, but sure why not. An example would be nice though