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Problem with Verilog and VHDL is widely known. This is why I proposed[1] to create a unified LLVM-like framework to prevent many projects from reinventing the w
by xvilka 7y ago
Problem with Verilog and VHDL is widely known. This is why I proposed[1] to create a unified LLVM-like framework to prevent many projects from reinventing the wheel, and be able to use each other's results.
[1] https://github.com/SymbiFlow/ideas/issues/19 https://github.com/SymbiFlow/ideas/issues/19
- Traster 7y agoAre you aware that Intel's OpenCL compiler for FPGA uses actual LLVM?
- xvilka 7y agoYes, but LLVM is not very suitable in general for FPGA/ASIC design. FIRRTL[1][2] looks much more complete and fit among various alternatives. [1] https://bar.eecs.berkeley.edu/projects/firrtl.html https://bar.eecs.berkeley.edu/projects/firrtl.html [2] https://github.com/freechipsproject/firrtl https://github.com/freechipsproject/firrtl