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I've done three ASICs using only schematics in the 1980s (back when 2.5 um was the bomb). I've done ASICs, FPGAs, but mostly full custom designs since then. A

I've done three ASICs using only schematics in the 1980s (back when 2.5 um was the bomb). I've done ASICs, FPGAs, but mostly full custom designs since then. And this article is wrong-headed on many levels. Verilog is an event-driven modeling language. It easily describes large collections of processes where a given process is triggered for reevaluation any time one of its inputs changes. That is what it was designed for back in the 80s. Using it for automatic synthesis of logic came later. If your mental model is that Verilog is an ISA then things will be very confusing. Programming language semantics and ISAs are two different things. Yes, the Verilog language is pretty ugly. But it allows low level modeling at the primitive level, even if that primitive is a single logic gate. And like any programming language, hierarchy is used to build useful abstractions for the particular problem domain.

lvoudour 7y ago
Seems like the author is arguing that when FPGAs are used for "computation" and not for prototyping or replacing ASICs for low volume production, there should be an ISA to abstract the gory details like in GPUs/CPUs, and Verilog is not an adequate abstraction in that regard because it's more like a programming language. Now, I may misinterpret the author's argument, but I don't understand the obsession over ISAs. It's a bit short sighted IMHO and, I agree with you, HDLs may not be elegant or pretty but they do their job just fine, ie. low level modeling at the primitive level. They are not programming languages. I also don't see how vendor locking fits with the rest of the narrative. Whatever intermediate abstraction the vendors offer (the author gives no examples which makes the post read more like a rant) it still won't expose the inner workings which (unlike CPUs/GPUs) are crucial for truly open FPGA development. Now should we strive for a better alternative, an evolution to FPGAs that benefit from an "ISA" type of abstraction? I'm not smart enough to visualize it, but sure why not. An example would be nice though
ncmncm 7y ago
The article is not about using Verilog to model ASICs. He even says himself it's fine for that. He wants to compute with FPGAs. So, if you're not interested in computing with FPGAs, you won't agree with him. Full Stop.
- dang 7y ago
  OK, we've added "for computing" to the title above.
petra 7y ago
If Verilog is your target, compile times will be too slow. This is better: "We describe a hybrid area estimation technique which uses template-level models and design-level artificial neural networks to account for effects from hardware place-and-route tools, including routing overheads, register and block RAM duplication, and LUT packing...We show that estimates average 4.8% error for logic resources, 6.1% error for runtimes, and are 279 to 6533 times faster than a commercial high-level synthesis tool." https://ieeexplore.ieee.org/document/7551387 https://ieeexplore.ieee.org/document/7551387 And based on this representation , they've built a high level language for FPGA accelerators, available to download: https://spatial-lang.org/ https://spatial-lang.org/

lvoudour 7y ago

Seems like the author is arguing that when FPGAs are used for "computation" and not for prototyping or replacing ASICs for low volume production, there should be an ISA to abstract the gory details like in GPUs/CPUs, and Verilog is not an adequate abstraction in that regard because it's more like a programming language. Now, I may misinterpret the author's argument, but I don't understand the obsession over ISAs. It's a bit short sighted IMHO and, I agree with you, HDLs may not be elegant or pretty but they do their job just fine, ie. low level modeling at the primitive level. They are not programming languages. I also don't see how vendor locking fits with the rest of the narrative. Whatever intermediate abstraction the vendors offer (the author gives no examples which makes the post read more like a rant) it still won't expose the inner workings which (unlike CPUs/GPUs) are crucial for truly open FPGA development. Now should we strive for a better alternative, an evolution to FPGAs that benefit from an "ISA" type of abstraction? I'm not smart enough to visualize it, but sure why not. An example would be nice though

ncmncm 7y ago

The article is not about using Verilog to model ASICs. He even says himself it's fine for that. He wants to compute with FPGAs. So, if you're not interested in computing with FPGAs, you won't agree with him. Full Stop.

dang 7y ago
OK, we've added "for computing" to the title above.

petra 7y ago

If Verilog is your target, compile times will be too slow. This is better: "We describe a hybrid area estimation technique which uses template-level models and design-level artificial neural networks to account for effects from hardware place-and-route tools, including routing overheads, register and block RAM duplication, and LUT packing...We show that estimates average 4.8% error for logic resources, 6.1% error for runtimes, and are 279 to 6533 times faster than a commercial high-level synthesis tool." https://ieeexplore.ieee.org/document/7551387 https://ieeexplore.ieee.org/document/7551387 And based on this representation , they've built a high level language for FPGA accelerators, available to download: https://spatial-lang.org/ https://spatial-lang.org/