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> I don't think it makes much sense trying to accomplish this on FPGAs; you're better off using CPUs, GPUs, or making something domain-specific like TPUs. I du
by wwwigham 7y ago
> I don't think it makes much sense trying to accomplish this on FPGAs; you're better off using CPUs, GPUs, or making something domain-specific like TPUs.
I dunno, we have a lot of libraries and frameworks who make it their purpose to efficiently run code on either a CPU or GPU (or TPU, if we're talking about things like tensorflow); a FPGA is conceptually just an extension of that except, ofc, that on-the-fly FPGA recompilation usually outweighs any performance benefits you'd get from using the FPGA based hardware accelerator, so the only reasonable uses are one and done layouts with occasional patches/updates. If we could get an FPGA gate pipeline that was as efficient as the modern shader pipeline, I think what we could use them for could expand greatly - imagine a tracing JIT that could dynamically load hot sequential code into an FPGA to speed it up, the same way we can load matrix ops into a GPU today.
With where FPGA toolchains are today, it just doesn't work _because_ the compilation process is so bad and slow, and nobody except the engineers within Xilinx and Altera even have a reasonable shot at making it better since both the compiler and the compilation target are closed. Part of it is simply that these compilation passes aren't really configurable (beyond expressing layout and pipelining preference) - if I could get near instant bitstream generation in exchange for 30% extra space used, I'd use that setting for all but my final builds, and strongly consider invoking it at runtime.
- TBF-RnD 7y agoI've been thinking about this for so long! I believe Intel did research on it with possible results. Are you interested in pursuing it?
- LargoLasskhyfv 7y agoHm. Are you aware of [1] https://www.microsoft.com/en-us/research/project/emips/ https://www.microsoft.com/en-us/research/project/emips/ & [2] https://blog.netbsd.org/tnf/entry/support_for_microsoft_emips_extensible https://blog.netbsd.org/tnf/entry/support_for_microsoft_emip... ? Especially the two papers which come up when you search like this? [3] https://duckduckgo.com/?q=microsoft+extensible+mips https://duckduckgo.com/?q=microsoft+extensible+mips MIPS-to-Verilog, Hardware Compilation for the eMIPS Processor Karl Meier, Alessandro Forin Microsoft Research September 2007 Technical Report MSR-TR-2007-128 Microsoft Research Microsoft Corporation One Microsoft Way Redmond, WA 98052 [4] https://www.microsoft.com/en-us/research/wp-content/uploads/2016/02/tr-2007-128.pdf https://www.microsoft.com/en-us/research/wp-content/uploads/... and EXTENSIBLE MICROPROCESSOR WITHOUT INTERLOCKED PIPELINE STAGES (eMIPS), THE RECONFIGURABLE MICROPROCESSOR A Thesis by RICHARD NEIL PITTMAN Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE May 2007 Major Subject: Computer Engineering [5] https://oaktrust.library.tamu.edu/bitstream/handle/1969.1/5976/etd-tamu-2007A-CECN-Pittman.pdf https://oaktrust.library.tamu.edu/bitstream/handle/1969.1/59...