The premise of the post seems to be that Verilog RTL is the lowest form of abstraction in which you can program an FPGA, and that everything lower is guarded by

The premise of the post seems to be that Verilog RTL is the lowest form of abstraction in which you can program an FPGA, and that everything lower is guarded by proprietary FPGA tools. That is simply not true. You can manually instantiate FPGA primitives (LUTs/BRAMs/DSPs) with all major FPGAs, and if you’re truly desperate you can add placement attributes to place these primitives exactly where you want them. That’s as close to the metal as I can imagine (other than specifying the actual routing network), and from there one could build up any abstraction level one desires.