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I'm annoyed this post ended with an open question. I was hoping it might at least have some ideas, as I do agree that verilog is a horrible abstraction layer.
by phire 7y ago
I'm annoyed this post ended with an open question. I was hoping it might at least have some ideas, as I do agree that verilog is a horrible abstraction layer.
However, I don't think an ISA for FPGA can exist, not one that that allows for quick synthesis.
Sure, you could drop down to a layer where everything is described as LUTs, FFs and routing; But you still need to run "place and route" before you can execute it, and that the expensive part of synthesis.
- gjvc 7y agoAgree. At the risk of sounding like a nihilist, such articles that ask more questions than they answer rarely raise any questions of insight, and this has the effect of making people forget the value of the whole article, given that the articles often end with the "open questions" section. IMHO. YMMV.
- skybrian 7y agoIt's a bit disappointing, but this is a blog post, not a research paper, so maybe the problem is with our expectations?
- dooglius 7y agoWith a title like "FPGAs Have the Wrong Abstraction", it rather suggests that the author has something better in mind.
- deleted 7y ago[deleted]
- tachyonbeam 7y agoIMO, if what you want is to accelerate computation, what you need is basically an FPGA with higher-level building blocks. Instead of an array of lookup tables, you want an array of what are essentially ALUs and registers. The abstraction should be something more akin to a dataflow graph, where you can route data from one unit to another. Yes, I know FPGAs already have adders, multipliers and registers inside them. My point is, they should have more of that. For computation, the focus needs to be on having as many of these useful high-level building blocks as possible, and making the routing of data between these blocks as easy as possible. For instance, routing 32-wide or 64-wide buses between these units, instead of individual wires. The "problem" with FPGAs is that they are trying to be able to emulate any ASIC. If what you want is a general-purpose computational accelerator, you need hardware that is a bit more high-level and more specialized. More tailored for that specific purpose.
- deleted 7y ago[deleted]
- gmueckl 7y agoMore ALUs reminds me of the GreenArrays chips: hundreds of really tiny cores arranged on grid, each one running a small program. Pretty weird stuff. And the canonical development tool is a very weird color forth environment.
- tachyonbeam 7y agoI saw a live presentation about greenarrays by its creator and wasn't impressed. His presentation was a long list of cool assembly-level tricks he had come up with to program his own chip, it seemed like he was trying to show off his skills to the audience. The chip has a very arcane design that is impractical to use, hence why it saw very little adoption.
- gmueckl 7y agoI only saw a friend of mine hacking that stuff once. Or at least he tried to. I don't actually know if he ever got to a point where he had something interesting running. I know that I would never put up with that color forth environment, though. Even though the GreenArrays design may be quite flawed, there mihht be use cases where the array of small cores idea could be put to use. I'm also remimded a bit of the XMOS multicore microcontrollers for some reason, although they are quite different. But the core link can work even between microcontroller packages, allowing the xreation of decently sized grids. But I can't think of a good use case for a large grid of those. Thus is more about nerworkimg microcontollers on an embedded context.
- monocasa 7y agoThe cadence hardware emulators are like that. Arrays of tiny processors that only do bitwise ops. They look like FPGAs to programmers though.