6 ms·
Note regarding Note: It actually has 16*16MB cache. The L3 is split into 16MB segments per CCX, and organized as a victim cache taking lines evicted from the 4
by Tuna-Fish 7y ago
Note regarding Note: It actually has 16*16MB cache. The L3 is split into 16MB segments per CCX, and organized as a victim cache taking lines evicted from the 4 local L2 caches. That is, a single core cannot ever write to more than 16.5MB of cache.
So there's not really any way to run system out of only cache, outside the tiny examples of early boot where all CPUs do this.
- ksec 7y agoThanks. Didn't come to my mind when I was writing that. So I stand corrected. I wonder if one day we put even more cache in the I/O Die. Or even Stacked DRAM directly on top of it.
- dr_zoidberg 7y agoThere have been a few Intel processors with "L4 cache" (meant to be used as iGPU memory, and only if unused work as L4 cache) as listed here [0]. Broadwell was the only generation to have desktop processors with the eDRAM chip sitting by the side of the processor. Now it's only on a few higher end ultrabook processors [1, 2] -- look for those listed with L4 cache. [0] https://en.wikichip.org/wiki/intel/microarchitectures/broadwell_(client)#Memory_Hierarchy https://en.wikichip.org/wiki/intel/microarchitectures/broadw... [1] https://en.wikipedia.org/wiki/Skylake_(microarchitecture)#Mobile_processors https://en.wikipedia.org/wiki/Skylake_(microarchitecture)#Mo... [2] https://en.wikipedia.org/wiki/Kaby_Lake#Mobile_processors https://en.wikipedia.org/wiki/Kaby_Lake#Mobile_processors