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Note that the 1P variant costs only $4,955, or under $80 per core. The consumer chips cost roughly $50/core, making this the flattest ramp I can personally reme
by reitzensteinm 7y ago
Note that the 1P variant costs only $4,955, or under $80 per core. The consumer chips cost roughly $50/core, making this the flattest ramp I can personally remember.
- yazr 7y agoDoes anyone have a graph of recent $/transistor progress? Its obvious that moore's law is stagnant, and clock speed is dead, etc, etc. But are we at least getting the same core size at a lower cost ?
- 0815test 7y agoI'm interested in this as well. Of course from a practical POV, especially with escalating NRE costs at recent nodes, we're clearly at a point where "getting the same core size at lower cost" is not going to be a thing unless you can afford to amortize that NRE over a huge volume of chips.
- ksec 7y ago>Does anyone have a graph of recent $/transistor progress? It wouldn't matter. You can't look at cost / transistor without factoring in Die Size and yield. Not to mention the cost of Higher Performance and Low Power Transistor are different. And the wafer price ( Cost / Transistor ) also exclude all the design cost and tooling around the node.
- ksec 7y agoThat is the brilliance of Chiplet strategy. Those 74nm 7nm Die are extremely cost effective. ( For reference they are even smaller than the SoC used in iPhone ) The 14nm I/O die ( 400mm2 ) seems to be most expensive part. I wonder what cost improvement could be done in that area. And Note: That 5K CPU has 256MB of L3 Cache. May be I could Run the OS not in RAM, but in Cache.
- 0815test 7y agoNote that Intel has also announced that they're going to use chiplets w/ 3D stacking for newer designs, starting in 2019. So this isn't something that's exclusive to AMD.
- ysleepy 7y agoBut AMD is again the innovator, just like with amd64, real dual-core, on-die memory controllers, hypertransport-style bus, on-die pcie controller, on-die gpu and so on.
- Tuna-Fish 7y agoNote regarding Note: It actually has 16*16MB cache. The L3 is split into 16MB segments per CCX, and organized as a victim cache taking lines evicted from the 4 local L2 caches. That is, a single core cannot ever write to more than 16.5MB of cache. So there's not really any way to run system out of only cache, outside the tiny examples of early boot where all CPUs do this.
- ksec 7y agoThanks. Didn't come to my mind when I was writing that. So I stand corrected. I wonder if one day we put even more cache in the I/O Die. Or even Stacked DRAM directly on top of it.
- dr_zoidberg 7y agoThere have been a few Intel processors with "L4 cache" (meant to be used as iGPU memory, and only if unused work as L4 cache) as listed here [0]. Broadwell was the only generation to have desktop processors with the eDRAM chip sitting by the side of the processor. Now it's only on a few higher end ultrabook processors [1, 2] -- look for those listed with L4 cache. [0] https://en.wikichip.org/wiki/intel/microarchitectures/broadwell_(client)#Memory_Hierarchy https://en.wikichip.org/wiki/intel/microarchitectures/broadw... [1] https://en.wikipedia.org/wiki/Skylake_(microarchitecture)#Mobile_processors https://en.wikipedia.org/wiki/Skylake_(microarchitecture)#Mo... [2] https://en.wikipedia.org/wiki/Kaby_Lake#Mobile_processors https://en.wikipedia.org/wiki/Kaby_Lake#Mobile_processors
- RantyDave 7y agoCoreboot has some interesting stuff around configuring the cache - it briefly runs cache-only so that would make a plausible starting point.