A public STM implementation has long been needed. In 2009, ITL/Qubes wrote about DRTM (Intel TXT, AMD SKINIT) and STM, https://invisiblethingslab.com/resource

A public STM implementation has long been needed. In 2009, ITL/Qubes wrote about DRTM (Intel TXT, AMD SKINIT) and STM, https://invisiblethingslab.com/resources/bh09dc/Attacking%20Intel%20TXT%20-%20paper.pdf https://invisiblethingslab.com/resources/bh09dc/Attacking%20... & https://www.blackhat.com/presentations/bh-dc-09/Wojtczuk_Rutkowska/BlackHat-DC-09-Rutkowska-Attacking-Intel-TXT-slides.pdf https://www.blackhat.com/presentations/bh-dc-09/Wojtczuk_Rut... > The late launch ... promises to effectively provide all the benefits of a computer restart without actually restarting it. It is hard to overemphasize the potential impact that a technology such as TXT could have on computer security ... We describe a practical attack that is capable of bypassing the TXT's trusted boot process ... As part of the attack we also discuss practical attacks on SMM memory ... Intel's remedy to malicious SMM handler is called STM, which stands for SMM Transfer Monitor. The purpose of STM is to sandbox the existing SMM handler by virtualizing it using VT-x and VT-d technologies. STM should be thought of as of a peer hypervisor to the VMM that is being loaded using late launch. STM is supposed to be measured during the late launch process ... no STM, as of today, is unfortunately available on the market, which yields our attack applicable to all current systems. One aim of our research ... is to stimulate developers to create an STM. The May 2019 version of Windows 10 added support ("SystemGuard") for DRTM-enabled hardware that could benefit from an STM, https://www.microsoft.com/security/blog/2018/04/19/introducing-windows-defender-system-guard-runtime-attestation/ https://www.microsoft.com/security/blog/2018/04/19/introduci... & https://www.platformsecuritysummit.com/2018/references/#systemguard https://www.platformsecuritysummit.com/2018/references/#syst... In 2018, NSA gave a presentation on their STM work, https://www.platformsecuritysummit.com/2018/speaker/myers/ https://www.platformsecuritysummit.com/2018/speaker/myers/ > We describe our work to demonstrate an enhanced SMI transfer monitor (STM) to provide protected execution services on the x86 platform ... Our STM enhancements create a protected execution capability by extending the STM to support additional VMs (PE/VM) From a coreboot developer, https://twitter.com/_zaolin_/status/1055474061428572162?s=21 https://twitter.com/_zaolin_/status/1055474061428572162?s=21 > We are currently implementing @intel #TXT and #SRTM measured boot support as part of Google's verified boot which can be used on all supported platforms in @coreboot_org