3 ms·
Isn't cmov just a normal instruction with 3 source operands? Or do you mean that the problem is having 3 instead of 2 source operands? Or that one of the oper
by devit 7y ago
Isn't cmov just a normal instruction with 3 source operands?
Or do you mean that the problem is having 3 instead of 2 source operands?
Or that one of the operands is the flag register on x86-like architecture? (but you can just use a normal register being nonzero)
- mellum 7y agoHaving 3 input operands is definitely an issue. In the Alpha EV6 architecture, it was decided only 2 inputs are supported, so a CMOV would need to be split into two actual instructions, the first of which setting the 65th bit of one of the operands to the result of the test and the other selecting the correct output. Thus, CMOV had 2 cycles latency and still required extra hardware resources to implement.
- ncmncm 7y agoThat one of the operands is the flag register, affected by other instructions you might want to schedule. RISC-V might have its own way to mitigate this.