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They are 8 core dies of a higher bin that would have been clocked the same (or possibly lower) in an equivalent 4 die Epyc part. Given the fact that it is a hig

They are 8 core dies of a higher bin that would have been clocked the same (or possibly lower) in an equivalent 4 die Epyc part. Given the fact that it is a higher bin, they are rare. What part of that illustrates they're defective, or that it legitimately costs more than if it was sold separately?

baybal2 7y ago
Very likely 6 cored dies simply have 1 or 2 defective cores that were either damaged during manufacturing or failed test. As for frequencies, modern day finfets can clock way way higher than planar devices, and are more limited by thermals than anything else.
- paulmd 7y ago
  That's the fairy-tale but most chips come off the line with all cores functional and the manufacturer disables some of the cores. Taken to the extreme - there just aren't that many chips with, say, 4 broken cores and yet the rest of the chip still works. Demand is highest for these cheap parts and supply is lowest, so you disable cores. The other thing is, these 12Cs are actually clocked significantly higher (and have much more cache enabled) than the lower-end parts. So these are not simply "bad silicon". Really this is a misnomer in general since there is a variety of ways silicon can be "bad". Bad clocks, damaged cache, damaged cores, etc etc. Binning gives you the opportunity to pick the best cores on a chip too. So if a chip had two cores that could only do 4 GHz but the rest of them could do 4.4 GHz or whatever, then all of them might be functional yet it might fail binning as a fast 8C chip, but you could disable the two derpy cores and ship it as a very fast 6C chip. The binning process is a deeply trade secret kinda thing, but is undoubtedly much more complex than people generally believe. It's not "top X% silicon becomes Epyc, next X% silicon becomes threadripper", etc. All that is known for sure is that AMD is very efficient at using every part of the buffalo.
  - baybal2 7y ago
    Clock ceiling became largely irrelevant with finfets, even most low end zen dies were hitting 3-3.5ghz when overclocked. Downbinned dies are clocked higher because they have more thermal leeway with 2 cores disabled.

baybal2 7y ago

Very likely 6 cored dies simply have 1 or 2 defective cores that were either damaged during manufacturing or failed test. As for frequencies, modern day finfets can clock way way higher than planar devices, and are more limited by thermals than anything else.

paulmd 7y ago
That's the fairy-tale but most chips come off the line with all cores functional and the manufacturer disables some of the cores. Taken to the extreme - there just aren't that many chips with, say, 4 broken cores and yet the rest of the chip still works. Demand is highest for these cheap parts and supply is lowest, so you disable cores. The other thing is, these 12Cs are actually clocked significantly higher (and have much more cache enabled) than the lower-end parts. So these are not simply "bad silicon". Really this is a misnomer in general since there is a variety of ways silicon can be "bad". Bad clocks, damaged cache, damaged cores, etc etc. Binning gives you the opportunity to pick the best cores on a chip too. So if a chip had two cores that could only do 4 GHz but the rest of them could do 4.4 GHz or whatever, then all of them might be functional yet it might fail binning as a fast 8C chip, but you could disable the two derpy cores and ship it as a very fast 6C chip. The binning process is a deeply trade secret kinda thing, but is undoubtedly much more complex than people generally believe. It's not "top X% silicon becomes Epyc, next X% silicon becomes threadripper", etc. All that is known for sure is that AMD is very efficient at using every part of the buffalo.
- baybal2 7y ago
  Clock ceiling became largely irrelevant with finfets, even most low end zen dies were hitting 3-3.5ghz when overclocked. Downbinned dies are clocked higher because they have more thermal leeway with 2 cores disabled.