Slightly off-topic but it's clear from the table that you can simulate any 2-in, 1-out gate with four bits of memory and two address lines. Which is exactly how

Slightly off-topic but it's clear from the table that you can simulate any 2-in, 1-out gate with four bits of memory and two address lines. Which is exactly how "gates" are implemented in FPGAs (albeit with more inputs and outputs).