3 ms·It's related to correcting DDR memory signal timing / clock skew.by vardump 7y agoIt's related to correcting DDR memory signal timing / clock skew.mehrdadn 7y agoOh it's the timing calibration thing that happens on initialization? Didn't realize that's called memory training haha cool!rurban 7y agoThat's probably what the unsigned data bodies are for. This data needs to be on the fast path.