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Scanning electron microscopy is necessary for analyzing wafers (we have one in the clean room at our university), but I'm not sure that the tunneling features a
by reemrevnivek 16y ago
Scanning electron microscopy is necessary for analyzing wafers (we have one in the clean room at our university), but I'm not sure that the tunneling features are necessary. From what I understand, you can usually see deep enough with the SEM to see the bottom of the wafer. He does mention the use of SEM and STM as separate topics, though, so I'm not sure that it was a slip of the tongue.
Take a look at this very accessible article on Sparkfun.com for some more information on analysis of circuit topologies. They're analyzing 4-year-old circuits.
http://www.sparkfun.com/news/384 http://www.sparkfun.com/news/384
- graphene 16y agoYes, SEM is usefeul for analyzing circuits, but STM (http://en.wikipedia.org/wiki/Scanning_tunneling_microscope http://en.wikipedia.org/wiki/Scanning_tunneling_microscope) is a completely different technique, which works at a scale about two orders of magnitude smaller. In a nutshell, SEM scans the sample with an electron beam and senses the reflected electrons to produce an image, while in STM, a metal probe is scanned across the surface at a very close distance, and variations in the tunneling current between the probe and the sample produce a topological map of the sample (because tunneling current depends strongly on distance). I don't see how you could use the same machine for both techniques, nor why you would need an STM in a semiconductor fab.