It needs to be slow, because each core will need to coordinate with all other contending cores. No matter what, the system must ensure all cores in the system

It needs to be slow, because each core will need to coordinate with all other contending cores. No matter what, the system must ensure all cores in the system have a coherent view of the cache line in question. So there must be communication involved. For example in MOESI protocol [0], it's not enough to have the cache line in exclusive state, you need to have it in owned state. So the core needs to broadcast to all other participating (contending) cores. You can simply saturate CPU internal core to core ring buses. Even worse between CPU sockets (multiple separate physical chips), because there's rather limited capacity to carry the coherency traffic. https://en.wikipedia.org/wiki/MOESI_protocol https://en.wikipedia.org/wiki/MOESI_protocol