3 ms·
Also important, not using a power of two sized ring is leaving lots of optimization on the table.
by banachtarski 7y ago
Also important, not using a power of two sized ring is leaving lots of optimization on the table.
- monocasa 7y agoEh, maybe/maybe not. This implementation requires a family big boy CPU with a really MMU; I'd be willing to bet that most of the extra latency of the divides are hidden in the memory access latencies.
- opencl 7y agoThere are two implementations described in this blog post and one of them is specifically designed to run on microcontrollers.
- banachtarski 7y agoCPUs are pipelined though so you can easily imagine many slots being operated on at once. Perhaps a better metric is the relative cost of the slot assignment against the the cost of the read/write operation. Not to mention the fact that elements may be in L1, in which case the penalty of additional cycles may actually be felt.